MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1736
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1736 of 2327
- Download datasheet (17Mb)
Operation
The sub-address only needs to be specified once for a multibyte transfer, as shown here.
Note that the sub-address must be sent for each start condition that initiates a transaction.
One must also provide the sub-address before reading bytes from the EEPROM. The
sub-address is transmitted from the master to the slave before it can receive data bytes. The
two transfers are joined into a single bus transaction through the use of a repeated start
condition (SR). Normally, a stop condition precedes a start condition. However, when a
start condition is preceded by another start condition, it is known as a repeated start (SR).
Note that the two-byte sub address is transferred using an SAD+W address, while the data
is received using a SAD+R address.
27.2.2.3 Master Mode Protocol
In master mode, the I
27.2.2.4 Clock Generation
The I
1736
ST
Table 27-9. I
ST
• If another device pulls the clock low before the I
• Once the low period has been counted, the I
ST
ST
then the I
period.
must then check to see if another device stills holds the line low, in which case it enters
a high wait state.
Table 27-8. I
2
SAD+W
C clock is generated from the APBX clock, as described in the register description.
Table 27-6. I
SAD+W
Table 27-7. I
SAD+W
SAD+W
SAK
2
2
C block immediately pulls the clock low as well and starts counting its low
C Transfer When Master is Receiving Multiple Bytes of Data from a Slave
2
C Transfer When Master is Receiving One Byte of Data from a Slave
SAK
SUB
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2
SAK
C Transfer When Master is Writing One Byte of Data to a Slave
2
SAK
2
C Transfer When Master is Writing Multiple Bytes to a Slave
C interface generates the clock and initiates all transfers.
SAK
SUB
SUB
SUB
SUB
SAK
SAK
SAK
SUB
SAK
SR
SUB
S A D + R
SAK
SUB
2
SAK
C block releases the clock line high, but
SAK
SR
2
C block has counted the high period,
DATA
DATA
SAK
SAD+R
MAK
SAK
DATA
SAK
DATA
Freescale Semiconductor, Inc.
MAK
DATA
DATA
SAK
DATA
SAK
NMAK
NMAK
SP
SP
SP
SP
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