MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1181
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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14.8.83 DRAM Control Register 88 (HW_DRAM_CTL88)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
DLL_CTRL_
REG_0_1
31
0
Field
Field
31 0
30
0
29
0
HW_DRAM_CTL88
28
0
Bits [14:8] = Holds the read DQS delay setting when the DLL is operating in normal mode. (dll_ctrl_reg_0_X
[28] = 'b0) Typically, this value is 1/4 of a clock cycle. Each increment of this field represents 1/128th of a
clock cycle.
Bits [7:0] = DLL Start Point Control. This value is loaded into the DLL at initialization and is the value at
which the DLL will begin searching for a lock. Each increment of this field represents 1/128th of a clock
cycle. This value MUST be >= 3.
All other bits undefined.
Controls the DLL bypass logic and holds the DLL start point and read DQS delay settings for data slice 1.
There is a separate dll_ctrl_reg_0_X parameters for each of the slices of data sent on the DFI data bus.
Bit [28] = DLL Bypass Control.
'b0 = Normal operational mode. In this mode, the DLL uses dll_ctrl_reg_0_X [14:8] for the read DQS and
dll_ctrl_reg_1_X [14:8] for clk_wr.
'b1 = Bypass Mode is on. In this mode, the DLL uses dll_ctrl_reg_0_X [23:15] for the read DQS and
dll_ctrl_reg_1_X [23:15] for clk_wr.
Bits [23:15] = Holds the read DQS delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X
[28] = 'b1)
Bits [14:8] = Holds the read DQS delay setting when the DLL is operating in normal mode. (dll_ctrl_reg_0_X
[28] = 'b0) Typically, this value is 1/4 of a clock cycle. Each increment of this field represents 1/128th of a
clock cycle.
Bits [7:0] = DLL Start Point Control. This value is loaded into the DLL at initialization and is the value at
which the DLL will begin searching for a lock. Each increment of this field represents 1/128th of a clock
cycle. This value MUST be >= 3.
All other bits undefined.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL87 field descriptions (continued)
24
0
23
0
HW_DRAM_CTL88 field descriptions
800E_0000h base + 160h offset = 800E_0160h
22
0
21
0
20
0
19
0
DLL_CTRL_REG_0_1
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1181
0
0
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