MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1319

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

One half-period later, valid master data is transferred to the MOSI line. Now that both
master and slave data have been set, the SSP_SCK master clock pin becomes low after one
further half SSP_SCK period. This means that data is captured on the falling edges and
propagated on the rising edges of the SSP_SCK signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SSn line is returned to its idle high state one SSP_SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSn signal must be
pulsed high between each data word transfer. This is because the slave select pin freezes
the data in its serial peripheral register and does not allow it to be altered if the PHASE bit
is logic 0. Therefore, the master device must raise SSPSFSSIN (the SSn pin in slave mode)
of the slave device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSn pin is returned to its idle state one SSP_SCK
period after the last bit has been captured.
17.5.6 Motorola SPI Format with Polarity=1, Phase=1
The transfer signal sequence for Motorola SPI format with POLARITY=1 and PHASE=1
is shown in
In this configuration, during idle periods:
Freescale Semiconductor, Inc.
• The SSP_SCK signal is forced high.
• SSn is forced high.
• The Transmit data line MOSI is arbitrarily forced low.
• When the SSP is configured as a master, the SSP_SCK pad is an output.
• When the SSP is configured as a slave, the SSP_SCK is an input.
Figure 17-7. Motorola SPI Frame Format with POLARITY=1 and PHASE=1
Figure
In
Figure
SSP_SCK
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
17-7, which covers both single and continuous transfers.
MOSI
MISO
SSn
17-7, Q is an undefined signal.
Q
MSB
MSB
Note
4 to 16 bits
Chapter 17 Synchronous Serial Ports (SSP)
LSB
LSB
Q
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