MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 885
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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- Download datasheet (17Mb)
Address:
10.8.24 Fractional Clock Control Register 0 (HW_CLKCTRL_FRAC0)
The FRAC0 control register provides control for PFD clock generation.
HW_CLKCTRL_FRAC0: 0x1B0
HW_CLKCTRL_FRAC0_SET: 0x1B4
HW_CLKCTRL_FRAC0_CLR: 0x1B8
Freescale Semiconductor, Inc.
Reset
Reset
CAN0_STATUS
CAN1_STATUS
STOP_CAN0
STOP_CAN1
Bit
Bit
W
W
RSRVD2
RSRVD1
R
R
Field
26 0
31
30
29
28
27
31
15
0
0
HW_CLKCTRL_FLEXCAN 8004_0000h base + 160h offset = 8004_0160h
30
14
1
0
Always set to zero (0).
If this bit is set to one (1'b1), the FLEXCAN0 will be stopped and all the clocks to FLEXCAN0 are gated off.
This read-only bit indicates FLEXCAN0 status. 1'b1: FLEXCAN0 is in STOP mode. 1'b0: FLEXCAN0 is in
NORMAL Mode.
If this bit is set to one (1'b1), the FLEXCAN1 will be stopped and all the clocks to FLEXCAN1 are gated off.
This read-only bit indicates FLEXCAN1 status. 1'b1: FLEXCAN1 is in STOP mode. 1'b0: FLEXCAN1 is in
NORMAL Mode.
Always set to zero (0).
29
13
1
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_FLEXCAN field descriptions
28
12
1
0
27
11
1
0
26
10
0
0
25
0
0
9
RSRVD1[15:0]
24
0
0
8
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
23
0
0
7
22
RSRVD1[26:16]
0
0
6
21
0
5
0
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
885
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