MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 390
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 390 of 2327
- Download datasheet (17Mb)
Programmable Registers
6.5.24 APBH DMA Channel 2 Command Register (HW_APBH_CH2_CMD)
The APBH DMA Channel 2 command register specifies the cycle to perform for the current
command chain item.
The command register controls the overall operation of each DMA command for this channel.
It includes the number of bytes to transfer to or from the device, the number of APB PIO
command words included with this command structure, whether to interrupt at command
completion, whether to chain an additional command to the end of this one and whether
this transfer is a read or write DMA transfer.
Address:
390
Reset
CMD_ADDR
Bit
W
R
Field
31 0
31
0
HW_APBH_CH2_CMD
30
0
Pointer to next command structure for channel 2.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBH_CH2_NXTCMDAR field descriptions
28
0
27
0
8000_4000h base + 200h offset = 8000_4200h
26
0
25
0
XFER_COUNT
24
0
Description
23
0
22
0
21
0
20
0
Freescale Semiconductor, Inc.
19
0
18
0
17
0
16
0
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