MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1754

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
1754
SEND_NAK_ON_
ACKNOWLEDGE
MULTI_MASTER
RETAIN_CLOCK
CLOCK_HELD
PRE_ACK
CLKGATE
SFTRST
RSVD2
RSVD1
LAST
Field
RUN
31
30
29
28
27
26
25
24
23
22
21
Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset
state.
0x0
0x1
This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
0x0
0x1
Set this bit to one to enable the I2C Controller operation. This bit is automatically set by DMA commands
that write to CTRL1 after the last PIO write of the DMA command. For Soft DMA operation, software can
set this bit to enable the controller.
0x0
0x1
Always set this bit field to zero.
Reserved for Freescale use.
Set this bit to one to cause a pending acknowledge bit (prior to DMA transfer) to be acknowledged. Set it
to zero to NAK the pending acknowledge bit. This bit is set to one by the slave search engine if the criteria
is met for acknowledging a slave address. Software can reset the bit to slave-not-acknowledge the address.
This bit defines the state of the i2c_data line during the address acknowledge bit time. The slave search
engine holds the clock at this point for a software decision. This bit has no effect when the presend start
option is selected.
0x0
0x1
Set this bit to one to cause the DMA transfer engine to send a NAK on the last byte.
0x0
0x1
Always set this bit field to zero.
Set this bit to one to enable the master state machine to monitor the start conditions generated by other
masters. The bus is assumed to be busy from the first start condition generated by another master until a
stop condition is generated.
0x0
0x1
This bit is set to one by the I2C controller state machines. It holds the I2C clock line low until cleared. It
must be cleared by firmware, either by CPU instructions or DMA PIO transactions. It is set high when a
slave address is matched by the slave controller. It is also set high at the end of a master or slave transaction
that had the RETAIN_CLOCK bit set high. Software should not set this bit to one.
0x0
0x1
Set this bit to one to retain the clock at the end of this transaction. This has the effect of holding the clock
low until the start of the next transaction.
0x0
0x1
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RUN — Allow I2C to operate normally.
RESET — Hold I2C in reset.
RUN — Allow I2C to operate normally.
NO_CLKS — Do not clock I2C gates in order to minimize power consumption.
HALT — No I2C command in progress.
RUN — Process a slave or master I2C command.
SNAK — slave not acknowledge when the held clock is released.
ACK — slave acknowledge when the held clock is released.
ACK_IT — Send an ACK on the last byte received.
NAK_IT — Send a NAK on the last byte received.
SINGLE — Assume we are the only master.
MULTIPLE — Enable multiple master bus busy monitoring from start detects.
RELEASE — Release the clock line.
HELD_LOW — The clock line is currently being held low.
RELEASE — Release the clock line after this data transfer.
HOLD_LOW — Hold the clock line low after this data transfer.
HW_I2C_CTRL0 field descriptions
Description
Freescale Semiconductor, Inc.