MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1106

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
The suffix "_oen" means the output enable signal is active low.
The start time and the end time of a output enable signal can be configured separately.
The start time and the end time can be adjusted by 1/4 clock cycle in unit.
To meet the timing requirement of the I/O circuits, the start time of each output enable must
be prior to it’s corresponding output signal, and, the end time must be later than it’s
corresponding signal. In another word, the output enable signal must be "wider" than the
output signal. The margin at start time is named "pre-amble" and the margin at end time is
named "post-amble". In the example of
= 1/4 cycle.
14.8 Programmable Registers
EMI Register Format Summary
1106
800E_000C
800E_001C
800E_002C
800E_003C
800E_0000
800E_0004
800E_0008
800E_0010
800E_0014
800E_0018
800E_0020
800E_0024
800E_0028
800E_0030
800E_0034
800E_0038
800E_0040
800E_0044
Absolute
address
(hex)
output enable for write data strobe.
DRAM Control Register 00 (HW_DRAM_CTL00)
AXI Monitor Control (HW_DRAM_CTL01)
DRAM Control Register 02 (HW_DRAM_CTL02)
DRAM Control Register 03 (HW_DRAM_CTL03)
DRAM Control Register 04 (HW_DRAM_CTL04)
DRAM Control Register 05 (HW_DRAM_CTL05)
DRAM Control Register 06 (HW_DRAM_CTL06)
DRAM Control Register 07 (HW_DRAM_CTL07)
DRAM Control Register 08 (HW_DRAM_CTL08)
DRAM Control Register 09 (HW_DRAM_CTL09)
AXI0 Debug 0 (HW_DRAM_CTL10)
AXI0 Debug 1 (HW_DRAM_CTL11)
AXI1 Debug 0 (HW_DRAM_CTL12)
AXI1 Debug 1 (HW_DRAM_CTL13)
AXI2 Debug 0 (HW_DRAM_CTL14)
AXI2 Debug 1 (HW_DRAM_CTL15)
DRAM Control Register 16 (HW_DRAM_CTL16)
DRAM Control Register 17 (HW_DRAM_CTL17)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_DRAM memory map
Figure
14-14, pre-amble = 1/2 cycle while post-amble
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Freescale Semiconductor, Inc.
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0010h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
14.8.10/1117
14.8.11/1118
14.8.12/1118
14.8.13/1119
14.8.14/1119
14.8.15/1120
14.8.16/1120
14.8.17/1121
14.8.18/1122
14.8.1/1111
14.8.2/1112
14.8.3/1113
14.8.4/1114
14.8.5/1114
14.8.6/1115
14.8.7/1115
14.8.8/1115
14.8.9/1116
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