MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 681

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

9.2.2.2 Pin Voltage Selection
Each GPIO (non-EMI) pin can be programmed to operate at either 1.8 V or 3.3 V by setting
the bit corresponding to that pin in one of the HW_PINCTRL_DRIVEx registers. The EMI
pins are capable of running at 1.5/1.8 V depending on the EMI_VDDIO voltage.
9.2.2.3 Pullup Selection
Several digital pins can be programmed to enable pullups by setting the appropriate bit in
one of the HW_PINCTRL_PULLx registers. Note that enabling the pullup will also disable
the internal gate keeper on that pin. The EMI pads do not have pullup selection, but do have
keeper disable capability.
Freescale Semiconductor, Inc.
• All clock pads have 8 and 16mA drive strength.
• All EMI pads have 5, 10 and 20 mA drive strengths.
The HW_PINCTRL_DRIVEx registers must be con gured prior
to the operation of the pins and cannot be changed mid-course
during active operation. Drive-strength options are provided to
optimize simultaneous switching output (SSO) noise. The majority
of GPIO pins must be programmed in 4-mA mode. For EMI pins,
the weakest mode should be used as long as the timing is met.
It is recommended that the drive strength of GPMI_RDn and
GPMI_WRn output pins be set to 8 mA. This will reduce the
transition time under heavy loads. Low transition times will be
important when NAND interface read and write cycle times are
below 30 ns. The other GPMI pins may remain at 4 mA, since
their frequency is only up to half that of GPMI_RDn and
GPMI_WRn.
The GPIO pad driver has two PMOS pullup drivers directly
connected to the 1.8 or 3.3-V power supply.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Note
Note
Note
Chapter 9 Pin Control and GPIO (PinCtrl)
681