MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 525

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.5.9 APBX DMA Channel 0 Buffer Address Register
The APBX DMA Channel 0 buffer address register contains a pointer to the data buffer for
the transfer. For immediate forms, the data is taken from this register. This is a byte address
which means transfers can start on any byte boundary.
This register holds a pointer to the data buffer in system memory. After the command values
have been read into the DMA controller and the device controlled by this channel, then the
DMA transfer will begin, to or from the buffer pointed to by this register.
EXAMPLE
Freescale Semiconductor, Inc.
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
COMMAND
RSVD1
RSVD0
CHAIN
11 8
Field
5 4
1 0
7
6
3
2
(HW_APBX_CH0_BAR)
Reserved, always set to zero.
A value of one indicates that the channel will wait for the end of command signal to be sent from the ABPX
device to the DMA before starting the next DMA command.
A value of one indicates that the channel will decrement its semaphore at the completion of the current
command structure. If the semaphore decrements to zero, then this channel stalls until software increments
it again.
Reserved, always set to zero.
A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the
current command, i.e. after the DMA transfer is complete.
A value of one indicates that another command is chained onto the end of the current command structure.
At the completion of the current command, this channel will follow the pointer in HW_APBX_CH0_CMDAR
to find the next command.
This bitfield indicates the type of current command:
00- NO DMA TRANSFER
01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master
write).
10- read transfer
11- reserved
0x0
0x1
0x2
HW_APBX_CH0_CMD field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
NO_DMA_XFER — Perform any requested PIO word transfers but terminate command before any
DMA transfer.
DMA_WRITE — Perform any requested PIO word transfers and then perform a DMA transfer from
the peripheral for the specified number of bytes.
DMA_READ — Perform any requested PIO word transfers and then perform a DMA transfer to the
peripheral for the specified number of bytes.
Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
Description
525