MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 822
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 822 of 2327
- Download datasheet (17Mb)
Programmable Registers
9.4.68 PINCTRL Bank 0 Interrupt Level/Edge Register
The PINCTRL Bank 0 Interrupt Level/Edge Register selects level or edge sensitivity for
interrupt requests for the pins in bank 0.
HW_PINCTRL_IRQLEVEL0: 0x1200
HW_PINCTRL_IRQLEVEL0_SET: 0x1204
HW_PINCTRL_IRQLEVEL0_CLR: 0x1208
HW_PINCTRL_IRQLEVEL0_TOG: 0x120C
This register selects level or edge detection for interrupt generation. Each pin in bank 0 that
is configured for interrupt generation can be independently set to interrupt on low level,
high level, rising edge, or falling edge by setting bits in this register and
HW_PINCTRL_IRQPOL0 (see below) appropriately.
Address:
Re-
822
set
Bit
W
R
IRQLEVEL
31
RSRVD1
RSRVD1
RSRVD1
0
IRQEN
31 21
31 29
Field
20 0
Field
28 0
30
0
29
0
(HW_PINCTRL_IRQLEVEL0)
HW_PINCTRL_IRQLEVEL0
28
0
Empty Description.
Each bit in this register corresponds to one of the 21 pins in bank 4:
1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT4.
0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT4.
Empty Description.
Each bit in this register corresponds to one of the 29 pins in bank 0:
1= Level detection;
0= Edge detection.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_PINCTRL_IRQLEVEL0 field descriptions
24
0
HW_PINCTRL_IRQEN4 field descriptions
23
0
22
0
21
0
8001_8000h base + 1200h offset = 8001_9200h
20
0
19
0
18
0
17
0
16
0
IRQLEVEL
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0
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