MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2057

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

33.2.1 Bus Interface Mechanisms
The LCDIF block has memory-mapped control, data and status registers. It provides two
efficient methods of transferring data to/from an external LCD controller or a digital video
encoder, the APB DMA slave and AXI bus master. In either mode of operation, the bus
interface portion of the block works off the HCLK domain, while the actual interface to
external display/encoder works off the CLK_DIS_LCDIFn domain. There are three main
FIFOs in the block datapath. The latency FIFO (LFIFO) in the write datapath is a 256 double
words deep synchronous FIFO that offers buffering against system bandwidth and latency.
Another FIFO in the write datapath, called TXFIFO, is a 16 words deep asynchronous FIFO
Freescale Semiconductor, Inc.
RXFIFO
32x16
LCDIF
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
DOTCLK LCD
System /
Interface
VSYNC/
Figure 33-1. LCDIF Top Level Diagram
EMI
AXI Master
38x16 TXFIFO
76x256 LFIFO
38x2 INTFIFO
APB Bridge
SRAM
HW_LCDIF_CTRL and
_DATA Registers and
APBH Master
To/From LCD Pins
AHB
DMA Slave
Shared APBH DMA
ARM CORE
Digital Video
Interface
APBH Ctrl
Osc. or PLL
24-MHz
Divide
XTAL
by m
Chapter 33 LCD Interface (LCDIF)
Divide
by n
Osc. or PLL
24-MHz
XTAL
CLK_DIS_LCDIFn
Domain
Domain
HCLK
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