MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 479
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 479 of 2327
- Download datasheet (17Mb)
Freescale Semiconductor, Inc.
Reset
NEXTCMDADDRVALID
WR_FIFO_EMPTY
Bit
RD_FIFO_EMPTY
W
R
WR_FIFO_FULL
RD_FIFO_FULL
BURST
SENSE
READY
RSVD1
15
0
LOCK
KICK
19 5
Field
REQ
END
31
30
29
28
27
26
25
24
23
22
21
20
14
0
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
This bit reflects the current state of the DMA Request Signal from the APB device
This bit reflects the current state of the DMA Burst Signal from the APB device
This bit reflects the current state of the DMA Kick Signal sent to the APB Device
This bit reflects the current state of the DMA End Command Signal sent from the APB Device
This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device
This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device
This bit reflects the current state of the DMA Channel Lock for a GPMI Channel.
This bit reflects the internal bit which indicates whether the channel's next command address is
valid.
This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
Reserved
HW_APBH_CH13_DEBUG1 field descriptions
12
0
11
0
RSVD1[15:5]
10
0
0
9
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
0
8
0
7
Description
0
6
5
0
4
0
STATEMACHINE
0
3
0
2
0
1
0
0
479
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