MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1322

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

SD/SDIO/MMC Mode
The SSP's SD/MMC controller can automatically perform a single block read/write or card
register operation with a single PIO setup and RUN. For example, the SD/MMC controller
can perform these steps with a single write to the PIO registers:
The SD/MMC controller is generally used with the DMA. Each DMA descriptor is set up
the SD/MMC controller to perform a single complex operation as exemplified above.
Multiple DMA descriptors can be chained to perform multiple card block transfers without
CPU intervention. A single DMA descriptor can also perform multiple card block transfers.
17.8.1 SD/MMC Command/Response Transfer
SD/MMC commands are written to the HW_SSP_CMDn registers and sent on the CMD
line. Command tokens consist of a start bit (0), a source bit (1), the actual command, which
is padded to 38 bits, a 7-bit CRC and a stop bit (1). The command token format is shown
in
SD/MMC cards transmit command words with the most significant bit first. After the card
receives the command, it checks for CRC errors or invalid commands. If an error occurs,
the card withholds the usual response to the command.
After transmitting the end bit, the SSP releases the CMD line to the high-impedance state.
A pullup resistor on the CMD node keeps it at the 1 state until the response packet is received.
The slave waits to issue a reply until the SCK line is clocking again.
After the SSP sends an SD/MMC command, it optionally starts looking for a response from
the card. It waits for the CMD line to go low, indicating the start of the response token.
Once the SSP has received the Start and Source bits, it begins shifting the response content
into the receive shift register. The SSP calculates the CRC7 of the incoming data.
1322
• Send command to the card.
• Receive response from the card.
• Check response for errors (and assert a CPU IRQ if there is an error).
• Wait for the DAT line(s) to be ready to transfer data (while counting for time-out).
• Transfer multiple blocks of data to/from the card.
• Check the CRC or CRC status of received/sent data (and assert IRQ if there is an error).
Table
CMD
Line
17-2.
Start
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 17-2. SD/MMC Command/Response Transfer
1 (Host)
Source
38-bit Command
Data
Freescale Semiconductor, Inc.
CRC7
CRC
End
1