MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 821
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 821 of 2327
- Download datasheet (17Mb)
9.4.67 PINCTRL Bank 4 Interrupt Mask Register (HW_PINCTRL_IRQEN4)
The PINCTRL Bank 4 Interrupt Mask Register contains interrupt enable masks for the pins
in bank 4.
HW_PINCTRL_IRQEN4: 0x1140
HW_PINCTRL_IRQEN4_SET: 0x1144
HW_PINCTRL_IRQEN4_CLR: 0x1148
HW_PINCTRL_IRQEN4_TOG: 0x114C
As described earlier in this chapter, any digital I/O pin can be used as an interrupt source.
This register masks the interrupt sources from the pins in bank 4. If a bit is set in this register
and the same bit is set in HW_PINCTRL_IRQSTAT4, an interrupt will be propagated to
the interrupt collector as interrupt GPIO4. For example, if this register contains 0x00000014,
then only bits 2 and 4 in HW_PINCTRL_IRQSTAT4 (corresponding to pins GPIO4[2] and
GPIO4[4]) will cause interrupts from bank 4.
Address:
Re-
Freescale Semiconductor, Inc.
Reset
set
Bit
W
R
Bit
W
31
RSRVD1
0
R
IRQEN
Field
30 0
31
30
0
15
0
29
0
HW_PINCTRL_IRQEN4
28
0
14
0
Empty Description.
Each bit in this register corresponds to one of the 31 pins in bank 3:
1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT3.
0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT3.
27
RSRVD1
0
26
0
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
12
0
HW_PINCTRL_IRQEN3 field descriptions
23
0
22
0
11
0
8001_8000h base + 1140h offset = 8001_9140h
21
0
20
10
0
0
19
0
18
0
0
9
17
0
IRQEN[15:0]
16
0
0
8
15
0
Description
14
0
7
0
13
0
0
12
6
0
11
0
IRQEN
Chapter 9 Pin Control and GPIO (PinCtrl)
5
0
10
0
0
9
4
0
0
8
0
7
0
3
0
6
0
5
0
2
0
4
3
0
0
1
0
2
0
1
0
0
821
0
0
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