MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2253

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor, Inc.
Reset
INTERRUPT_
SEQUENCE_
INTERRUPT_
INTERRUPT_
OVERFLOW_
INTERRUPT_
INTERRUPT_
INTERRUPT_
STATUS_CLR
FIFO_READ_
INTERRUPT_
SEQUENCE_
ADC_DONE_
END_ONE_
END_ONE_
TIMEOUT_
Bit
W
RSRVD1
ENABLE
ENABLE
ENABLE
ENABLE
R
STATUS
EMPTY
FIFO_
Field
25 6
CLR
31
30
29
28
27
26
5
4
15
0
14
0
When set to 1'b1,the HSADC asserts interrupt when one sequence is finished.When set to 1'b0,the HSADC
does not assert interrupt when one sequence is finished.
When set to 1'b1,the HSADC asserts interrupt when all sequences are finished.When set to 1'b0,the HSADC
does not assert interrupt when all sequences are finished.
When set to 1'b1,the HSADC asserts interrupt when FIFO overflow occurs.When set to 1'b0,the HSADC
does not assert interrupt when FIFO overflow occurs.
When set to 1'b1,the HSADC asserts interrupt when timeout occurs.When set to 1'b0,the HSADC does not
assert interrupt when timeout occurs.
When set to 1'b1,clear the HSADC interrupt.This bit can be auto cleared.
When set to 1'b1,clear all the HSADC interrupt status.This bit can be auto cleared.
Reserved.
FIFO read empty. 1 means there is no data in the FIFO, 0 means there is data in the FIFO.
This bit is set to one upon one sequence is finished.It is ANDed with its corresponding interrupt enable bit
to request an interrrupt.Can be cleared by INTERRUPT_STATUS_CLR bit.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_HSADC_CTRL1 field descriptions
RSRVD1[15:6]
11
0
10
0
0
9
0
8
Description
0
7
0
6
5
1
Chapter 37 High-Speed ADC (HSADC)
4
0
0
3
0
2
0
1
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0
0