MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 357

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor, Inc.
8000_46C0
8000_46D0
8000_4640
8000_4650
8000_4660
8000_4670
8000_4680
8000_4690
8000_46A0
8000_46B0
8000_46E0
8000_46F0
8000_4700
8000_4710
8000_4720
8000_4730
8000_4740
8000_4750
8000_4760
8000_4770
8000_4780
Absolute
address
(hex)
APBH DMA channel 12 Current Command Address Register
(HW_APBH_CH12_CURCMDAR)
APBH DMA channel 12 Next Command Address Register
(HW_APBH_CH12_NXTCMDAR)
APBH DMA channel 12 Command Register
(HW_APBH_CH12_CMD)
APBH DMA channel 12 Buffer Address Register
(HW_APBH_CH12_BAR)
APBH DMA channel 12 Semaphore Register
(HW_APBH_CH12_SEMA)
AHB to APBH DMA channel 12 Debug Information
(HW_APBH_CH12_DEBUG1)
AHB to APBH DMA channel 12 Debug Information
(HW_APBH_CH12_DEBUG2)
APBH DMA Channel 13 Current Command Address Register
(HW_APBH_CH13_CURCMDAR)
APBH DMA Channel 13 Next Command Address Register
(HW_APBH_CH13_NXTCMDAR)
APBH DMA Channel 13 Command Register
(HW_APBH_CH13_CMD)
APBH DMA Channel 13 Buffer Address Register
(HW_APBH_CH13_BAR)
APBH DMA Channel 13 Semaphore Register
(HW_APBH_CH13_SEMA)
AHB to APBH DMA Channel 13 Debug Information
(HW_APBH_CH13_DEBUG1)
AHB to APBH DMA Channel 13 Debug Information
(HW_APBH_CH13_DEBUG2)
APBH DMA channel 14 Current Command Address Register
(HW_APBH_CH14_CURCMDAR)
APBH DMA channel 14 Next Command Address Register
(HW_APBH_CH14_NXTCMDAR)
APBH DMA channel 14 Command Register
(HW_APBH_CH14_CMD)
APBH DMA channel 14 Buffer Address Register
(HW_APBH_CH14_BAR)
APBH DMA channel 14 Semaphore Register
(HW_APBH_CH14_SEMA)
AHB to APBH DMA channel 14 Debug Information
(HW_APBH_CH14_DEBUG1)
AHB to APBH DMA channel 14 Debug Information
(HW_APBH_CH14_DEBUG2)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBH memory map (continued)
Register name
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
00A0_0000h
00A0_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
6.5.100/474
6.5.101/474
6.5.102/477
6.5.103/477
6.5.104/478
6.5.105/480
6.5.106/481
6.5.107/481
6.5.108/482
6.5.109/484
6.5.110/485
6.5.111/485
6.5.112/488
6.5.92/466
6.5.93/466
6.5.94/467
6.5.95/469
6.5.96/470
6.5.97/470
6.5.98/473
6.5.99/473
Section/
page
357