MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1578

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
25.6.1 Module Configuration Register (HW_CAN_MCR)
This register defines global system configurations, such as the module operation mode (e.g.,
low power)and maximum message buffer configuration.Most of the fields in this register
can be accessed at any time, except the MAXMB field, which should only be changed while
the module is in Freeze Mode. The default value of this register is 0x5890000f.
The MCR defines global system configurations such as the module operation mode (for
example, low-power mode) and maximum message buffer configuration. The MAXMB
field must only be changed while the module is in freeze mode: all other fields in this register
can be accessed at any time.
Address:
1578
Reset
Reset
8003_202C
8003_2030
8003_2034
8003_2080
8003_2880
Absolute
address
Bit
Bit
W
W
(hex)
R
R
MDIS
Field
31
MDIS
31
15
0
0
RSVD2
HW_CAN_MCR
Interrupt Flags 2 Register (HW_CAN_IFLAG2)
Interrupt Flags 1 Register (HW_CAN_IFLAG1)
Glitch Filter Width Register (HW_CAN_GFWR)
CAN Messager Buffer Registers (HW_CAN_MBn)
Rx Individual Mask Registers (HW_CAN_RXIMRn)
FRZ
30
14
1
0
This bit controls whether CAN is enabled or not.When disabled, CAN shuts down the clocks to the CAN
Protocol Interface and Message Buffer Management sub-modules. This is the only bit in MCR not affected
by soft reset.
1 Disable the FlexCAN module
FEN
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
AEN
28
12
1
0
8003_2000h base + 0h offset = 8003_2000h
HW_CAN memory map (continued)
Register name
NOT_
RDY
HW_CAN_MCR field descriptions
27
11
1
0
RSVD1
26
10
0
0
25
0
0
9
IDAM
FRZ_
ACK
24
0
0
8
Description
SUPV
23
1
0
7
RSVD0
SLF_
WAK
22
0
0
6
(in bits)
Width
32
32
32
32
32
21
0
5
0
Access
LPM_
R/W
R/W
R/W
R/W
R/W
ACK
20
1
4
0
Freescale Semiconductor, Inc.
Reset value
0000_0000h
0000_0000h
0000_007Fh
0000_0000h
0000_0000h
19
0
1
3
MAXMB
18
0
1
2
SRX_
25.6.11/1588
25.6.12/1589
25.6.13/1590
25.6.14/1590
25.6.15/1591
DIS
17
0
1
1
Section/
page
BCC
16
0
1
0