MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1741
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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27.2.2.6 Slave Mode Protocol
The I
DMA, and some supporting software to intervene in the transaction.
The flow chart for slave mode is shown in
Freescale Semiconductor, Inc.
• At device start-up, all the registers are reset so that the state is known from that time
• Once the I
• Once this is detected, the slave reads in eight bits and checks against its programmed
• If it is the programmed address, an acknowledgement is sent; otherwise, the slave does
• Once the slave search engine detects an address, it holds the clock line and interrupts
• Next the software checks the RW bit.
onward.
on the I2C_SCL and I2C_SDA lines.
device address (which defaults to 0x86 == 7'b1000011) to see if a master device is
trying to start a transfer with i.MX28 operating as a slave.
not acknowledge and returns to state IDLE.
the CPU.
2
C slave protocol is handled by a combination of I
2
Figure 27-7. I
C slave search engine is enabled, the slave waits to detect a start condition
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2
Release Held Clock
C Master Mode Flow Chart-Send Stop States
I2c_sda_en = 1
I2c_sda_en = 0
Reset post send
Wait for stop
setup time
Reset Run,
Wait for
Run
SEND
STOP
Figure
Release sda
Force sda to zero
27-8.
2
C functional block hardware, the
Chapter 27 Inter IC (I2C)
1741
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