MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2060

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
of the same color for each pixel. If the input frame has lesser bits per pixel than the display,
for example, 24 bpp input frame going to 16 bpp LCD, LCDIF will drop the LSBs of each
color to go to the lower resolution. LCDIF also has the capability to support delta pixel
displays by swizzling the R, G and B colors of each pixel in the odd and even lines of the
frame separately by programming the ODD_LINE_PATTERN and the
EVEN_LINE_PATTERN bitfields. This operation occurs after the RGB-to-RGB color
space conversion operation.
LCDIF also supports RGB to YCbCr 4:2:2 color space conversion. This is useful in the
DVI mode since the TV encoder requires input in YCbCr 4:2:2 format. The
HW_LCDIF_CSC* registers have complete programmability over the CSC coefficients
and offsets. The values must be written into these registers in the signed two's complement
format.
The following list shows how the different input/output combinations can be obtained:
2060
• WORD_LENGTH=1 indicates that the input is 8-bit data. This is most likely going to
• WORD_LENGTH=0 implies the input frame buffer is RGB 16 bits per pixel.
• WORD_LENGTH=2 indicates that input frame buffer is RGB 18 bits per pixel, that
• WORD_LENGTH=3 indicates that the input frame-buffer is RGB 24 bits per pixel
be used for sending commands in MPU interface, or maybe a grayscale image. Any
combination of BYTE_PACKING_FORMAT [3:0] is permissible.
Limitation: H_COUNT must be a multiple of the sum of BYTE_PACKING_FORMAT
[3], BYTE_PACKING_FORMAT [2], BYTE_PACKING_FORMAT [1] and
BYTE_PACKING_FORMAT [0]. LCD_DATABUS_WIDTH must be 1, indicating
an 8-bit data bus.
DATA_FORMAT_16_BIT field determines the pixels are RGB 555 or RGB 565.
Limitation: BYTE_PACKING_FORMAT [3:0] should be 0x3 or 0xC if there is only
one pixel per word. If there are two pixels per word, it should be 0xF and H_COUNT
will be restricted to be a multiple of 2 pixels.
is, RGB 666. The valid RGB values can be left-aligned or right-aligned within a 32-bit
word. The alignment of the valid 18 bits within a word is indicated by the
DATA_FORMAT_18_BIT bit.
Limitation: BYTE_PACKING_FORMAT can be 0x7, 0xE or 0xF. Packed pixels are
not supported in this case. H_COUNT can be any number.
(RGB 888). If BYTE_PACKING_FORMAT [3:0] is 0x7, it indicates that there is only
one pixel per 32-bit word and there is no restriction on H_COUNT.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.