MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1059
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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13.3.35 DCP Version Register (HW_DCP_VERSION)
Read-only register indicating implemented version of the DCP.
This register returns the debug data from the selected debug index source.
Address:
Re-
Freescale Semiconductor, Inc.
Reset
set
Bit
W
R
Bit
W
31
ENABLE
0
R
MAJOR
MINOR
FLUSH
31 24
23 16
BASE
STEP
Field
31 2
Field
15 0
30
1
0
0
15
0
29
0
MAJOR
HW_DCP_VERSION
28
0
14
0
Page Table Base Address. The page table must be word aligned and the pointer should reference a page
table in the standard ARM format.
Page Table Flush control. To flush the TLB, write this bit to a 1 then back to a 0.
Page Table Enable control. Virtual addressing will only be used when this bit is set to a 1. Disabling the
page table will not flush any cached entries, so software should write the FLUSH high and enable LOW
when updating page tables.
Fixed read-onlyl value reflecting the MAJOR version of the design implementation.
Fixed read-onlyl value reflecting the MINOR version of the design implementation.
Fixed read-onlyl value reflecting the stepping of version of the design implementation.
27
0
26
0
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
1
24
0
12
0
HW_DCP_PAGETABLE field descriptions
23
0
HW_DCP_VERSION field descriptions
8002_8000h base + 430h offset = 8002_8430h
22
0
11
0
21
0
MINOR
20
10
0
0
19
0
BASE[15:2]
18
0
0
9
17
0
16
0
1
8
15
0
Description
Description
14
0
7
0
13
0
0
12
6
0
11
0
5
0
10
0
Chapter 13 Data Co-Processor (DCP)
0
9
4
0
STEP
0
8
0
7
0
3
0
6
0
5
0
2
0
4
3
0
0
1
0
2
0
1
1059
0
0
0
0
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