MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 819
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 819 of 2327
- Download datasheet (17Mb)
Address:
Re-
9.4.65 PINCTRL Bank 2 Interrupt Mask Register (HW_PINCTRL_IRQEN2)
The PINCTRL Bank 2 Interrupt Mask Register contains interrupt enable masks for the pins
in bank 2.
HW_PINCTRL_IRQEN2: 0x1120
HW_PINCTRL_IRQEN2_SET: 0x1124
HW_PINCTRL_IRQEN2_CLR: 0x1128
HW_PINCTRL_IRQEN2_TOG: 0x112C
As described earlier in this chapter, any digital I/O pin can be used as an interrupt source.
This register masks the interrupt sources from the pins in bank 2. If a bit is set in this register
and the same bit is set in HW_PINCTRL_IRQSTAT2, an interrupt will be propagated to
the interrupt collector as interrupt GPIO2. For example, if this register contains 0x00000014,
then only bits 2 and 4 in HW_PINCTRL_IRQSTAT2 (corresponding to pins GPIO2[2] and
GPIO2[4]) will cause interrupts from bank 2.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
31
31
0
0
IRQEN
Field
31 0
RSRVD1
30
30
0
0
29
29
0
0
HW_PINCTRL_IRQEN1
HW_PINCTRL_IRQEN2
28
28
0
0
Each bit in this register corresponds to one of the 32 pins in bank 1:
1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT1.
0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT1.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
HW_PINCTRL_IRQEN1 field descriptions
23
23
0
0
22
22
0
0
8001_8000h base + 1110h offset = 8001_9110h
8001_8000h base + 1120h offset = 8001_9120h
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
IRQEN
16
16
0
0
15
15
0
0
Description
IRQEN
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
Chapter 9 Pin Control and GPIO (PinCtrl)
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
819
0
0
0
0
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