MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2161
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Address:
34.4.13 Source 0 Scale Offset Register (HW_PXP_S0OFFSET)
S0 Scale Offset. This register provides the initial scale offset for the S0 (video) buffer.
The X and Y offset provides the ability to access the source image with a per pixel or per
sub-pixel granularity. To shift the source input image by a single pixel, for example, a value
of 0x200 (for 8x8 block size) would be loaded into this offset field. For a 8x8 block size,
0x200 (or 1/8), will provide a fixed offset of 1 pixel for the entire PXP operation. With this
setting for 16x16 block size, the value of 0x200 will provide a fixed offset of 2 pixels since
1/8 of a 16 pixel block is 2. The fixed offset values can also be used for sub-pixel adjustments
in the bilinear scaling filter. For example, when scaling an image down by a factor of 2, an
initial offset of 0x0 would result in sub-sampling every other pixel. If a fixed offset of 0x100
(1/16) with 8x8 block size selected is programmed, all pixels are used in scaling the final
output pixel value.
EXAMPLE
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
W
W
YSCALE
XSCALE
R
R
RSVD2
RSVD1
30 16
Field
14 0
RSVD2
RSVD1
31
15
31
15
0
0
HW_PXP_S0SCALE
30
14
0
0
Reserved, always set to zero.
This is a three bit integer and 12 bit fractional representation (###.####_####_####) of the Y scaling factor
for the S0 source buffer. The maximum value programmed should be 4 since scaling down by a factor
greater than 4 is not supported.
Reserved, always set to zero.
This is a three bit integer and 12 bit fractional representation (###.####_####_####) of the X scaling factor
for the S0 source buffer. The maximum value programmed should be 4 since scaling down by a factor
greater than 4 is not supported.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
1
1
HW_PXP_S0SCALE field descriptions
8002_A000h base + B0h offset = 8002_A0B0h
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
YSCALE
XSCALE
Description
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
Chapter 34 Pixel Pipeline (PXP)
19
0
0
3
18
0
0
2
17
0
0
1
2161
16
0
0
0
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