MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2243

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

37.3.1 Trigger Modes
This block can be triggered to start the conversion of analog source by three modes: the
first mode is software trigger mode which is to be triggered by ARM to configure a register
in this block; the second mode is to be triggered by a trigger pulse which is generated by
the PWM block with big flexibility; the third is to be triggered by an input pin from external
sources to support some general user cases.
The trigger signal is active high. The duration of the active high pulse needs to be longer
than one AHB clock cycle. The trigger signal needs to be de-asserted once the ADC is
started. So, it is recommended to assert just one cycle for PWM trigger mode. For external
trigger mode, the trigger signal should last for more than one AHB clock cycle. Due to
synchronization issue, in all the three trigger modes there will be two AHB clock cycles
and two operation clock cycles delay between the trigger pulse and the start of sampling
when the delay cycles are configured as 0. Note that for PWM trigger mode, the trigger
pulse is generated by operation clock, so the delay cycles should be three operation cycles.
Please refer to the
timing of analog ADC interface.
Freescale Semiconductor, Inc.
Figure 37-2. Clock paths of the PWM and High-Speed ADC blocks
Sensor control signals
Clock Block
Figure 37-3
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
PWM
for the timing of PWM trigger mode and
32MHz
Trigger signal
AHB clock
200MHz
Linear image sensor
Clock for ADC divider 288MHz
HSADC
Sampling clock32MHz
Sample data
Ctrl signals
Analog pixel data
Chapter 37 High-Speed ADC (HSADC)
ADC
Figure 37-4
for the
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