MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1894

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
29.9.54 ENET SWI Port 0 Priority resolution configuration
Port 0 Priority resolution configuration. Defines which priority information should be used
for priority resolution
1894
IPV4_SELECT
PRIORITY_
PRIORITY_
PRIORITY_
ADDRESS
RSRVD0
PORT2
PORT1
PORT0
30 15
14 13
12 11
Field
10 9
7 0
8
(HW_ENET_SWI_PRIORITY_CFG0)
When set during register writes, the IPv6 select and address bits are stored in the register only and the
priority bits are ignored and not written into the addressed table.
When the register is read, the priority bits represent the value read from the table always.
Reserved bits. Write as 0.
The priority information to write into the addressed table entry.
These 2 bits represent the output priority selected when the frame is received on port 2.
When reading from the register, the bits show the value from the addressed table entry (address from last
write operation).
The priority information to write into the addressed table entry.
These 2 bits represent the output priority selected when the frame is received on port 1.
When reading from the register, the bits show the value from the addressed table entry (address from last
write operation).
The priority information to write into the addressed table entry.
These 2 bits represent the output priority selected when the frame is received on port 0.
00=priority 0 (will be forwarded to output queue 0) 01=priority 1 (output queue 1) 10=priority 2 (output queue
2) 11=priority 3 (output queue 3)
When reading from the register, the bits show the value from the addressed table entry (address from last
write operation).
If set during a write, the IPv4 table is accessed. Valid address values range from 0 to 63.
If cleared, the IPv6 table is accessed. Valid address values range from 0 to 255.
The address of the priority entry to read or write for a frame received on port n.
The IPv4 priority table has 64 entries. The IPv6 table has 256 entries.
HW_ENET_SWI_IP_PRIORITY field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.