MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1464

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
21.2 Operation
The role of the performance monitor in an AXI system is to collect real time bus transaction
statistics, including transaction average and maximum latency, total data bandwidth, and
total active cycles. The statistics collection can be configured for single master or multiple
masters on the same AXI bus, and can be enabled for either read or write transactions.
There is one AXI bus in the i.MX28 system which has DCP, PXP, LCDIF and BCH.
AXI protocol supports out-of-order transaction completion. In i.MX28, out-of-order
transaction is programmable in EMI. Tag ID is used to trace each transaction and match
the data phase with the correct address phase. Performance Monitor supports out-of-order
transactions. AXI protocol separates the address/control phase and data phase, and has the
ability to issue multiple outstanding addresses. It gives an ID tag to every transaction across
the interface, which consists 4-bit master ID and 4-bit subID. Every master has its own
unique master ID, and each master could have up to 16 sub IDs, which means up to 16
outstanding address phases.
PerfMon collects the accumulated latency on cycle counts and number of transfers, the
average latency can be calculated by dividing the total latency over number of transfers.
Since the AXI protocol separates the address and data phases, the address and data phases
could be overlapped, and individual data phase could overlap with multiple address phase.
Statistics on total cycles, total data transfer in bytes will be collected as well. All statistics
are collected for either read or write transactions, which could be switched by the enable
bit in the control register.
To calculate the maximum latency and support out-of-order transaction, PerfMon needs to
cache the tag ID for all the outstanding requests. The potential number of outstanding
requests depends on how deep the command queue in the memory controller(EMI) which
includes two level of command queues. A scoreboard will be implemented to match the tag
ID of the ongoing data phase with the ID from the outstanding requests. PerfMon snapshots
the master ID(8 bits), burst length(4 bits), burst type(2 bits), burst size(3 bits) for the content
register of maximum latency, but no transfer address(32 bits).
Registers in PerfMon are accessible through APBH bridge, and PerfMon registers sits on
APBH clock domain. Shade registers are added for the coherence among statistics/status
registers, and the snapshot bit in PerfMon control register will trigger the shade register
being filled at the same cycle for these registers: total transfers, total latency, maximum
latency, content register for max_latency, total data bytes, total active cycles, and total
cycles.
Various interrupts supported in this module are as follows:
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1464
Freescale Semiconductor, Inc.