MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1668

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
26.4.8 ENET MAC MIB Control/Status Register (HW_ENET_MAC_MIBC)
Address:
1668
Reset
Reset
Reset
MII_SPEED
HOLDTIME
Bit
Bit
Bit
DIS_PRE
W
W
W
RSRVD0
RSRVD1
R
R
R
31 11
Field
10 8
6 1
MIB_
7
0
DIS
15
31
15
0
1
0
HW_ENET_MAC_MIBC
MIB_
IDLE
14
30
14
0
1
0
RSRVD0[15:11]
Reserved bits. Write as 0.
The IEEE802.3 Clause 22 defines a minimum of 10ns for the holdtime on the MDIO output. Depending on
the host bus frequency the setting may need to be increased. The following
Bit 10:8: MDIO hold time setting: 000 : 1 pclk cycle (default) 001 : 2 pclk cycles 010 : 3 pclk cycles 011 : 4
pclk cycles 100 : 5 pclk cycles 101 : 6 pclk cycles 110 : 7 pclk cycles 111 : 8 pclk cycles
Asserting this bit causes preamble (32 1s) not to be prepended to the MII management frame. The MII
standard allows the preamble to be dropped if the attached PHY device(s) does not require it.
MII_SPEED controls the frequency of the MII management interface clock (Signal mdc) relative to the internal
bus clock (pclk). A value of 0 in this field turns off the mdc and leaves it in low voltage state. Any non-zero
value results in the mdc frequency of 1/(MII_SPEED × 2) of the internal bus frequency (Clock pclk).
Reserved bits. Write as 0.
13
29
13
0
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
28
12
0
0
0
HW_ENET_MAC_MSCR field descriptions
11
27
11
0
0
0
800F_0000h base + 64h offset = 800F_0064h
10
26
10
0
0
0
HOLDTIME
25
0
0
0
9
9
RSRVD0[15:0]
24
0
0
0
8
8
Description
DIS_
PRE
23
0
RSRVD0[28:16]
0
0
7
7
22
0
0
0
6
6
21
5
0
0
5
0
MII_SPEED
20
4
0
0
4
0
Freescale Semiconductor, Inc.
19
0
0
0
3
3
18
0
0
0
2
2
17
0
0
0
1
1
16
0
0
0
0
0