MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1225

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

14.8.166 DRAM Control Register 177 (HW_DRAM_CTL177)
This is a DRAM configuration register.
Freescale Semiconductor, Inc.
Reset
ADD_ODT_CLK_
ADD_ODT_CLK_
ADD_ODT_CLK_
W2W_SAMECS_
SAMETYPE_
DIFFTYPE_
DIFFTYPE_
Bit
W
SAMECS
R
DIFFCS
DIFFCS
RSVD4
RSVD3
RSVD2
RSVD1
31 28
27 24
23 20
19 16
15 12
11 8
Field
DLY
7 3
2 0
15
0
14
0
RSVD2
Always write zeroes to this field.
Additional delay to insert between same transaction types to different chip selects to meet ODT timing
requirements.
Defines the number of additional clocks of delay to insert between commands of the same type (read to
read, write to write) to different chip selects to meet ODT timing requirements.
Always write zeroes to this field.
Additional delay to insert between different transaction types to the same chip select to meet ODT timing
requirements.
Defines the number of additional clocks of delay to insert between commands of different types (read to
write, write to read) to the same chip select to meet ODT timing requirements.
Always write zeroes to this field.
Additional delay to insert between different transaction types to different chip selects to meet ODT timing
requirements.
Defines the number of additional clocks of delay to insert between commands of different types (read to
write, write to read) to different chip selects to meet ODT timing requirements.
Always write zeroes to this field.
Additional delay to insert between writes and writes to the same chip select.
Defines the number of additional clocks of delay to insert between two write commands to the same chip
select.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_DRAM_CTL176 field descriptions
ADD_ODT_CLK_DIFFTYPE_
11
0
10
0
DIFFCS
0
9
0
8
Description
0
7
0
6
Chapter 14 External Memory Interface (EMI)
RSVD1
5
0
4
0
0
3
W2W_SAMECS_DLY
0
2
0
1
1225
0
0