MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2097

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

33.4.12 LCDIF VSYNC Mode and Dotclk Mode Control Register4
This register is used to control the DOTCLK mode of the block.
This register determines the active data in each horizontal line in the DOTCLK mode. Note
that the total number of active horizontal lines in the DOTCLK mode is the same as the
V_COUNT bitfield in the HW_LCDIF_TRANSFER_COUNT register.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
DOTCLK_DLY_
SIGNALS_ON
VALID_DATA_
DOTCLK_H_
Bit
Bit
W
W
RSRVD0
R
R
SYNC_
31 29
28 19
Field
17 0
CNT
SEL
18
DOTCLK_DLY_SEL
31
15
0
0
HW_LCDIF_VDCTRL4
(HW_LCDIF_VDCTRL4)
30
14
0
0
This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out
of the LCD_DOTCK pin. 0 = 2ns; 1=4ns;2=6ns;3=8ns. Remaining values are reserved.
Reserved bits, write as 0.
Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals
should be active atleast one frame before the data transfers actually start and remain active atleast one
frame after the data transfers end. The hardware does not count the number of frames automatically. Rather,
the VSYNC edge interrupt can be monitored by software to count the number of frames that have occured
after this bit is set and then the RUN bit can be set to start the data transactions. This bit must always be
set in the DOTCLK mode of operation, and it must be set in the VSYNC mode of operation when VSYNC
signal is an output.
Total number of CLK_DIS_LCDIFn cycles on each horizontal line that carry valid data in DOTCLK mode.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_LCDIF_VDCTRL4 field descriptions
27
11
0
0
8003_0000h base + B0h offset = 8003_00B0h
26
10
0
0
DOTCLK_H_VALID_DATA_CNT[15:0]
25
0
0
9
24
RSRVD0
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
Chapter 33 LCD Interface (LCDIF)
20
0
4
0
19
0
0
3
18
0
0
2
DOTCLK_H_
DATA_CNT
17
0
0
1
VALID_
[17:16]
2097
16
0
0
0