MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2019

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

31.7.41 Endpoint Control 1 Register (HW_USBCTRL_ENDPTCTRL1)
Register HW_USBCTRL_ENDPTCTRL1 is the control register for endpoint 1 in a device.
CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction
is disabled then the unused direction type must be changed from the default control-type to
any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause
undefined behavior for the data PID tracking on the active endpoint/direction.
Freescale Semiconductor, Inc.
RSVD2
RSVD1
Field
RXE
RXT
RXS
6 4
3 2
7
1
0
Bit reserved and should be read as zeroes.
RX Endpoint Enable.
1 = Enabled.
Endpoint0 is always enabled.
Reserved.
Bit reserved and should be read as zeroes.
RX Endpoint Receive Type.
Endpoint0 is fixed as a Control endpoint.
0
Reserved.
RX Endpoint Stall.
0 = Endpoint OK (default).
1 = Endpoint Stalled.
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. It will
continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt
of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.
Note: There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware
continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However,
should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually
write this stall bit until it is set OR until a new SETUP has been received by checking the associated
ENDPTSETUPSTAT bit.
HW_USBCTRL_ENDPTCTRL0 field descriptions (continued)
CONTROL — Control.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 31 USB High-Speed On-the-Go Host Device Controller
Description
2019