MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2073
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Chapter 33 LCD Interface (LCDIF)
signal is based on the CLK_DIS_LCDIFn (make sure VSYNC_PULSE_WIDTH_UNIT =
VSYNC_PERIOD_UNIT = 0 and VSYNC_ONLY = 1) and it is determined by the
VSYNC_PERIOD, VSYNC_PULSE_WIDTH and VSYNC_POL fields in
HW_LCDIF_VDCTRL0-4 registers. The SYNC_SIGNALS_ON bit in
HW_LCDIF_VDCTRL4 register must be set if the target requires the VSYNC signal to be
generated by LCDIF. If the WAIT_FOR_VSYNC_EDGE bit in HW_LCDIF_CTRL register
is set, it indicates that the hardware should wait until it sees the leading VSYNC edge before
starting the data transfer. The VERITCAL_WAIT_CNT indicates the number of
CLK_DIS_LCDIFn cycles from the leading VSYNC edge after which data transfer will be
started on the interface.
In the VSYNC interface mode, the HW_LCDIF_CTRL_ BYPASS_COUNT bit must be
0. The RUN bit is cleared automatically once the LCDIF has received/transmitted all the
data as per the HW_LCDIF_TRANSFER_COUNT register and has completed the transfer
to the panel. The current transfer can be cancelled/aborted if the RUN bit is manually made
0.
33.2.7.1 Code Example to initialize LCDIF in VSYNC mode
// Note: Common initialization steps in
Initializing the LCDIF
must also be
// executed along with the following code
BF_CS1 (LCDIF_CTRL, DATA_SELECT, 1); // 0 if sending command, 1 if sending data. Note that
//the idle state for LCD_RS signal is high, regardless of the programming of the DATA_SELECT
//register.
BF_CS1 (LCDIF_CTRL, MODE86, 8080_MODE);
BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 0); //Must be 0 in MPU mode
BF_CS1 (LCDIF_CTRL1, BUSY_ENABLE, 0);
BF_CS4 (LCDIF_TIMING, CMD_HOLD, 2, CMD_SETUP, 2, DATA_HOLD, 2, DATA_SETUP, 2);
//Values
//based on CLK_DIS_LCDIFn frequency and timing requirements of controller. Note that these
register
//must be non-zero for the MPU and VSYNC modes.
BF_CS2 (LCDIF_TRANSFER_COUNT, H_COUNT, 320, V_COUNT, 240);//For a 320 RGB x 240 display
//The following section indicates setting up the VSYNC signal timing when VSYNC is an output
BF_CS1 (LCDIF_VDCTRL0, VSYNC_OEB, 0); //Making VSYNC signal an output
BF_CS1 (LCDIF_VDCTRL4, VSYNC_ONLY, 1); //Only need to generate VSYNC signal
BF_CS1 (VDCTRL0, VSYNC_POL, 0); //Setting the polarity of VSYNC signal to be low during
//VSYNC_PULSE_WIDTH time
BF_CS2 (LCDIF_VDCTRL0, VSYNC_PERIOD_UNIT, 0, VSYNC_PULSE_WIDTH_UNIT, 0);
BF_CS2 (LCDIF_VDCTRL1, VSYNC_PERIOD, 400000, VSYNC_PULSE_WIDTH, 100);//Frame display rate in
//terms of number of CLK_DIS_LCDIFns.
BF_CS2 (LCDIF_VDCTRL2, HSYNC_PULSE_WIDTH, 0, HSYNC_PERIOD, 0);
BF_CS1 (LCDIF_VDCTRL3, VERTICAL_WAIT_CNT, 50);
BF_CS1 (LCDIF_VDCTRL4, SYNC_SIGNALS_ON, 1);
BF_CS2 (LCDIF_CTRL, VSYNC_MODE, 1, WAIT_FOR_VSYNC_EDGE, 1); //set WAIT_FOR_VSYNC_EDGE if
//software wishes to transfer the next frame after the VSYNC edge occurs.
BF_CS1 (LCDIF_CTRL, RUN, 1);
The LCDIF is now ready to receive data through DMA writes to the HW_LCDIF_DATA
register or fetch data directly from memory as a bus master. When LCDIF is done
transmitting H_COUNT x V_COUNT pixels, it will stop, turn off the RUN bit and assert
the cur_frame_done interrupt.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
2073
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