MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1313

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

17.2 External Pins
#id-54331/id-33763
The pin control interface on the i.MX28 provides all digital pins with selectable output drive
strengths. In addition, all SSP data pins have selectable 47-K pullup resistors, and SSP
command pins have 10-K pullups. Configuring the SSP_CMD pad to connect to the
internal 10-K pullup is recommended for SD/SDIO/MMC modes during the Card_ID
phase. After the Card_ID phase, the 10-K pullup should be disabled, and the weaker
external 47-K pullup takes over. The SSP_DATA pads also can be configured to connect
to an internal 47-K pullup, which is required for SD/SDIO/MMC modes.
17.3 Bit Rate Generation
The serial bit rate is derived by dividing down the internal clock SSPCLK. The clock is
first divided by an even prescale value, CLOCK_DIVIDE, from 2 to 254, which is
programmed in HW_SSP_TIMING. The clock is further divided by a value from 1 to 256,
which is 1 + CLOCK_RATE, where CLOCK_RATE is the value programmed in
HW_SSP_TIMING.
Freescale Semiconductor, Inc.
SSP_DETECT
SSP_DATA0
SSP_DATA1
SSP_DATA2
SSP_DATA3
SSP_DATA4
SSP_DATA5
SSP_DATA6
SSP_DATA7
SSP_CMD
SSP_SCK
Pin Name
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
lists the SSP pin placements for all supported modes.
MOTOROLASPI
MOSI
MISO
Mode
SSn0
SSn1
SSn2
SCK
Table 17-1. SSP Pin Matrix
WinBONDSPI
HOLDn (IO3)
WPn (IO2)
DO (IO1)
DI (IO0)
Mode
SSn0
SSn1
SSn2
CLK
TI SSIMode
MOSI
MISO
CLK
SSn
Chapter 17 Synchronous Serial Ports (SSP)
SD/SDIO/MMC/ Modes
CARD_DETECT
DATA1/IRQ
DATA0
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
CMD
CLK
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