MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1377
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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- Download datasheet (17Mb)
Address:
Re-
19.4.13 Digital Control Debug Read Test Register (HW_DIGCTL_DBGRD)
The Digital Control Debug Read Test Register is a read-only test value register.
This register is used for debugging purposes.
EXAMPLE
Address:
Re-
19.4.14 Digital Control Debug Register (HW_DIGCTL_DBG)
The Digital Control Debug Register is a read-only test value register.
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
COMPLEMENT
31
31
0
0
VALUE
Field
31 0
Field
31 0
30
30
0
1
ElapsedTime = StartTime - EndTime;
debug_value = HW_DIGCTL_DBGRD_RD();
29
29
0
1
HW_DIGCTL_MICROSECONDS 8001_C000h base + C0h offset = 8001_C0C0h
HW_DIGCTL_DBGRD
28
28
0
1
This register maintains a 32-bit counter that increments at a 1-microsecond rate. The 1-MHz clock driving
this counter is derived from the 24.0-MHz crystal oscillator. The count value is not preserved over
power-downs. The 32-bit value wraps in less than two hours.
This read-only bit field always reads back the one's complement of the value in HW_DIGCTL_DBG.
27
27
0
1
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
HW_DIGCTL_MICROSECONDS field descriptions
0
24
24
0
0
HW_DIGCTL_DBGRD field descriptions
23
23
0
1
22
22
0
0
8001_C000h base + D0h offset = 8001_C0D0h
21
21
0
0
20
20
0
1
19
19
0
1
18
18
0
0
COMPLEMENT
17
17
0
1
VALUE
16
16
0
0
15
15
// WARNING, handle rollover in real software
0
1
Description
Description
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
14
14
0
0
13
13
0
1
12
12
0
1
11
11
0
1
10
10
0
1
0
0
9
9
0
0
8
8
0
1
7
7
0
1
6
6
0
0
5
5
0
1
4
4
3
0
3
1
0
1
2
2
0
1
1
1
1377
0
0
0
0
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