MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1961

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Chapter 31 USB High-Speed On-the-Go Host Device Controller
USB0 is capable of supplying VBUS, while USB1 is for connection to on-system (on-board)
connectivity peripherals such as cellular modems and no support of VBUS.
31.3 USB Programmed I/O (PIO) Target Interface
The PIO interface is on an AHB slave of the USB controller. It allows the ARM processor
to access the configuration, control, and status registers. There are identification registers
for hardware configuration parameters and operational registers for control and status.
31.4 USB DMA Interface
The DMA is a master AHB interface that allows USB data to be transferred to/from the
system memory. The data in memory is structured to implement a software framework
supported by the controller. For a device controller, this structure is a linked-list interface
that consists of queue heads and pointers that are transfer descriptors. The queue head is
where transfers are managed. It has status information and location of the data buffers. The
hardware controller's PIO registers enable the entire data structure, and once USB data is
transferred between the host, the status of the transfer is updated in the queue head, with
minimal latency to the system.
For a host controller, there is also a linked-list interface. It consists of a periodic frame list
and pointers to transfer descriptors. The period frame list is a schedule of transfers. The
frame list points to the data buffers through the transfer descriptors. The hardware controller's
PIO registers enable the data structure and manage the transfers within a USB frame. The
period frame list works as a sliding window of host transfers over time. As each transfer is
completed, the status information is updated in the frame list.
31.5 USB UTM Interface
The USB UTM interface on the i.MX28 implements the specification that allows USB
controllers to interface with the USB PHY. Please refer to the USB 2.0 Transceiver Macrocell
Interface (UTMI) Specification, Version 1.05, for additional details:
http://www.intel.com/technology/usb/spec.htm
31.5.1 Digital/Analog Loopback Test Mode
Since the UTM has to operate at high frequencies (480 MHz), it has a capacity to self-test.
A pseudo-random number generator transmits data to the receive path, and data is compared
for validity. In the digital loopback, the data transfer only resides in the UTM. It checks for
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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