MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 334
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 334 of 2327
- Download datasheet (17Mb)
Programmable Registers
HW_ICOLL_INTERRUPT127_SET: 0x914
HW_ICOLL_INTERRUPT127_CLR: 0x918
HW_ICOLL_INTERRUPT127_TOG: 0x91C
This register provides a mechanism to specify the priority associated with an interrupt bit.
In addition, this register controls the enable and software generated interrupt. WARNING:
Modifying the priority of an enabled interrupt may result in undefined behavior. You should
always disable an interrupt prior to changing its priority.
EXAMPLE
HW_ICOLL_INTERRUPT127_SET(0,0x00000001);
Address:
334
Reset
Reset
Bit
Bit
SOFTIRQ
W
W
RSRVD1
ENABLE
R
R
ENFIQ
Field
31 5
4
3
2
31
15
0
0
HW_ICOLL_INTERRUPT127
0910h
30
14
0
0
Always write zeroes to this bitfield.
Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through
the main IRQ FSM and priority logic.
0x0
0x1
Set this bit to one to force a software interrupt.
0x0
0x1
Enable the interrupt bit through the collector.
0x0
0x1
29
13
0
0
DISABLE — Disable
ENABLE — Enable
NO_INTERRUPT — turn off the software interrupt request.
FORCE_INTERRUPT — force a software interrupt
DISABLE — Disable
ENABLE — Enable
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ICOLL_INTERRUPT127 field descriptions
28
12
0
0
27
11
0
0
RSRVD1[15:5]
8000_0000h base + 910h offset = 8000_
26
10
0
0
25
0
0
9
RSRVD1[31:16]
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
PRIORITY
17
0
0
1
16
0
0
0
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