MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1993
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1993 of 2327
- Download datasheet (17Mb)
31.7.24 Endpoint List Address Register (Device Controller mode)
In Device Controller mode, this register contains the address of the top of the endpoint list
in system memory. Bits [10:0] of this register cannot be modified by the system software
and will always return a 0 when read. The memory structure referenced by this physical
memory pointer is assumed 64-byte. This is a read/write register. Writes must be DWORD
writes.
Address:
Re-
31.7.25 Embedded TT Asynchronous Buffer Status and Control Register
This register contains parameters needed for internal TT operations. This register is not
used in the device controller operation. This is a read/write register. Writes must be DWORD
writes.
Freescale Semiconductor, Inc.
set
Bit
W
R
31
EPBASE
0
RSVD
31 11
RSVD
Field
Field
10 0
4 0
30
0
29
0
HW_USBCTRL_ENDPOINTLISTADDR 8008_0000h base + 158h offset = 8008_
0158h
(HW_USBCTRL_ENDPOINTLISTADDR)
(Host Controller mode) (HW_USBCTRL_TTCTRL)
28
0
HW_USBCTRL_ASYNCLISTADDR field descriptions (continued)
Reserved.
These bits are reserved and their value has no effect on operation.
Endpoint List Pointer (Low).
These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up
to 32 Queue Heads (QH). (i.e., one queue head per endpoint and direction.)
Reserved.
These bits are reserved and their value has no effect on operation.
27
0
HW_USBCTRL_ENDPOINTLISTADDR field descriptions
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
22
EPBASE
0
21
0
20
0
19
0
18
0
17
0
Chapter 31 USB High-Speed On-the-Go Host Device Controller
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
RSVD
0
5
0
4
3
0
0
2
0
1
1993
0
0
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