MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 849

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

The clk_h branch can be further divided by the dynamic clock frequency adjustment logic,
(hw_clkctrl_emi_sync_mode_en = 0 only). When all the system clk_h components are not
busy and their respective busy signals are inactive, the clk_h branch is further divided down
by the value in the hw_clkctrl_hbus register. The frequency reduction of the clk_h branch
saves overall power consumption. Note, the dynamic clock frequency adjustment logic
should not be enabled when clk_emi is synchronous with clk_h.
10.2.3.2 CLK_EMI
The external memory interface domain is called clk_emi. This clock can be asynchronous
to clk_h to achieve the highest possible clock rate for the EMI interface, or synchronously
to minimize the incurred latency for CPU access to external DRAM. This option is provided
to tradeoff the optimization of performace for systems that are dependent on memory access
latency or throughput.
When the hw_clkctrl_emi_sync_mode_en bit is set to 1, clk_h is synchronous and edge
aligned with the emi clock and clk_p. The emi clock dividers will set the frequency of clk_h
and clk_emi domains when synchronous mode is selected. In synchronous mode, the dynamic
clock frequency adjust logic should be disabled. This is required since DRAM devices
cannot operate correctly with changing clock frequencies.
10.2.3.3 System Clocks
All reference clock domains used in the CLKCTRL are driven by replicated instances of
the PFD pre dividers in the analog module. These PFD reference clocks drive replicated
instances of a single digital clock divider design to create all system clocks. The following
sections describe the features of the digital clock dividers and how these drives can be used
to create clocks throughout the system. The CLKCTRL structural diagram should be used
with the digital clock divider description to understand how clocks are generated in the
i.MX28 system.
10.3 CLKCTRL Digital Clock Divider
The digital clock divider that is used to drive all the functional clock domains has three
modes of operation. These include:
Freescale Semiconductor, Inc.
• Integer divide mode
For example, to achieve a 8:3 clk_p:clk_h clock ratio, set the div field to 0.01100 which
represents (0*1/2) + (1*1/4) + (1*1/8) + (0*1/16) + (0*1/32). Note, fractional divide
can not be used when clk_emi is synchronous with clk_h.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 10 Clock Generation and Control (CLKCTRL)
849