MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2302

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
38.5.17 LRADC Scheduling Delay 3 (HW_LRADC_DELAY3)
The LRADC scheduling delay 3 register controls one delay operation. At the end of this
delay, this channel can trigger one or more LRADC channels or one or more Scheduling
delay channels .
HW_LRADC_DELAY3: 0x100
HW_LRADC_DELAY3_SET: 0x104
HW_LRADC_DELAY3_CLR: 0x108
HW_LRADC_DELAY3_TOG: 0x10C
The LRADC Delay Channel provides control by which LRADC channels and delay channels
(including itself) may be triggered. The triggering of the selected delay and LRADC
channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It
is possible to use delay channels chained together to configure dependent timing of channel
conversions as in the example provided in introduction to this block. A delay channel may
also be configured to trigger itself. In this case, it could be used to simultaneously trigger
2302
LOOP_COUNT
TRIGGER_
TRIGGER_
LRADCS
RSRVD2
DELAYS
DELAY
31 24
23 21
19 16
15 11
KICK
Field
10 0
20
Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel.
This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC
channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered.
The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE.
Reserved
Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or
TRIGGER_DELAYS will start.
Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel.
This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels
can be triggered at the same time, including the one that issues the trigger. This can have the effect of
automatically retriggering a delay channel.
This bit field specifies the number of times this delay counter will count down and then trigger its designated
targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is
set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC
and/or delay channels.
ERRATA: TA1 and TA2 silicon revisions do not correctly support the LOOP_COUNT field, do not use.
This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another
delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single event.
This counter operates on a 2KHz clock derived from crystal clock.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LRADC_DELAY2 field descriptions
Description
Freescale Semiconductor, Inc.