MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1132

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
14.8.27 DRAM Control Register 29 (HW_DRAM_CTL29)
This is a DRAM configuration register.
Address:
Re-
1132
set
Bit
ACTIVE_AGING
W
R
AGE_COUNT
COMMAND_
31
CS_MAP
0
RSVD2
RSVD1
RSVD4
RSVD3
15 12
31 28
27 24
23 19
11 8
Field
Field
7 1
RSVD4
30
0
0
29
0
HW_DRAM_CTL29
28
0
Always write zeroes to this field.
Initial value of individual cmd aging counters for cmd aging.
Holds the initial value of the command aging counters associated with each command in the command
queue. When using the placement logic to fill the command queue, the command aging counters decrement
one each time the master aging-rate counter counts down the number of cycles in the age_count parameter.
Always write zeroes to this field.
Enable command aging in the command queue.
Enables aging of commands in the command queue when using the placement logic to fill the command
queue.
The total number of cycles required to decrement the priority value on a command by one is the product of
the values in the age_count and command_age_count parameters.
'b0 = Disabled
'b1 = Enabled
Always write zeroes to this field.
Defines which chip selects are active.
Sets the mask that determines which chip select pins are active, with each bit representing a different chip
select. The user address chip select field will be mapped into the active chip selects indicated by this
parameter in ascending order from lowest to highest. This allows the EMI to map the entire contiguous user
address into any group of chip selects. Bit [0] of this parameter corresponds to chip select [0], bit [1]
corresponds to chip select [1], etc. The number of chip selects, the number of bits set to 1 in this parameter,
must be a power of 2.
Always write zeroes to this field.
27
0
CS_MAP
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL28 field descriptions (continued)
24
0
23
0
HW_DRAM_CTL29 field descriptions
800E_0000h base + 74h offset = 800E_0074h
22
0
RSVD3
21
0
20
0
19
0
18
0
COLUMN_
SIZE
17
0
16
0
15
0
Description
Description
14
0
RSVD2
13
0
12
0
11
0
10
0
ADDR_
PINS
0
9
0
8
Freescale Semiconductor, Inc.
0
7
RSVD1
0
6
0
5
0
4
3
0
APREBIT
0
2
0
1
0
0