MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2154
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Programmable Registers
34.4.3 Output Frame Buffer Pointer (HW_PXP_OUTBUF)
Output Framebuffer Pointer. This register points to the beginning of the output frame buffer.
This pointer is used for progressive format and field 0 when generating interlaced output.
This register is used by the logic to point to the current output location for the output frame
buffer.
EXAMPLE
HW_PXP_OUTBUF_WR( buffer );
Address:
Re-
34.4.4 Output Frame Buffer Pointer #2 (HW_PXP_OUTBUF2)
Output Framebuffer Pointer #2. This register points to the beginning of the output frame
buffer for eitherfield 1 when generating interlaced output or for the UV buffer when in YUV
2-plane output modes. Both interlaced output AND 2-plane output modes are not supported.
This register is NOT used as the pointer to the 2nd buffer when in LCDIF_HANDSHAKE
mode.
This register is used by the logic to point to the current output location for the field 1 or UV
output frame buffer.
EXAMPLE
HW_PXP_OUTBUF_WR( field0 );
HW_PXP_OUTBUF2_WR( field1 ); // buffer for interlaced field 1
2154
set
Bit
W
R
31
0
ADDR
Field
31 0
30
0
29
0
HW_PXP_OUTBUF
28
0
Current address pointer for the output frame buffer. The address MUST be word-aligned for proper PXP
operation.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_PXP_OUTBUF field descriptions
8002_A000h base + 20h offset = 8002_A020h
22
// buffer for interlaced field 0
0
21
0
20
0
19
0
18
0
17
0
ADDR
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0
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