MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1316

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Motorola SPI Mode
Figure 17-2. Motorola SPI Frame Format (Single Transfer) with POLARITY=0 and PHASE=0
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the FIFO, the start of the transmission
is signified by the SSn master signal being low. This causes slave data to be enabled onto
the MISO input line of the master, and enables the master MOSI output pad.
One-half SSP_SCK period later, valid master data is transferred to the MOSI pin. Now that
both the master and slave data have been set, the SSP_SCK master clock pin goes high after
one further half SSP_SCK period.
The data is now captured on the rising and propagated on the falling edges of the SSP_SCK
signal.
In the case of a single word transmission, after all bits of the data word have been transferred,
the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSn signal must be
pulsed high between each data word transfer. This is because the slave select pin freezes
the data in its serial peripheral register and does not allow it to be altered if the PHASE bit
is logic 0. Therefore, the master device must raise the SSn pin of the slave device between
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• The SSP_SCK signal is forced low.
• SSn is forced high.
• The Transmit data line MOSI is arbitrarily forced low.
• When the SSP is configured as a master, SSP_SCK is an output.
• When the SSP is configured as a slave, SSP_SCK is an input.
Figure 17-3. Motorola SPI Frame Format with POLARITY=0 and PHASE=0
SSP_SCK
MOSI/MISO
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
SSP_SCK
MISO
MOSI
SSn
SSn
LSB
MSB
MSB
MSB
4 to 16 bits
4 to 16 bits
LSB
LSB
LSB
MSB
Freescale Semiconductor, Inc.
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