MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 832

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
9.4.79 PINCTRL Bank 1 Interrupt Status Register
The PINCTRL Bank 1 Interrupt Status Register reflects pending interrupt status for the pins
in bank 1.
HW_PINCTRL_IRQSTAT1: 0x1410
HW_PINCTRL_IRQSTAT1_SET: 0x1414
HW_PINCTRL_IRQSTAT1_CLR: 0x1418
HW_PINCTRL_IRQSTAT1_TOG: 0x141C
This register reflects the pending interrupt status for pins in bank 1. Bits in this register are
automatically set by hardware when an interrupt condition (level high, level low, rising
edge, or falling edge) occurs on a bank 1 pin which has been enabled as an interrupts source
in the HW_PINCTRL_PIN2IRQ1 register. Software may clear any bit in this register by
writing a 1 to the bit at the SCT clear address, e.g., HW_PINCTRL_IRQSTAT1_CLR.
Status bits for pins configured as level sensitive interrupts cannot be cleared unless either
the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt
source by clearing its bit in HW_PINCTRL_PIN2IRQ1. If a bit is set in this register, and
the corresponding bit is also set in the HW_PINCNTRL_IRQEN1 mask register, then the
GPIO1 interrupt will be asserted to the interrupt collector.
Address:
Re-
832
set
Bit
W
R
31
IRQSTAT
0
Field
31 0
30
0
29
0
(HW_PINCTRL_IRQSTAT1)
HW_PINCTRL_IRQSTAT1
28
0
Each bit in this register corresponds to one of the 32 pins in bank 1:
0= No interrupt pending;
1= Interrupt pending.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_PINCTRL_IRQSTAT1 field descriptions
23
0
22
0
21
0
8001_8000h base + 1410h offset = 8001_9410h
20
0
19
0
18
0
17
0
IRQSTAT
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0