MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 67
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Section Number
Freescale Semiconductor, Inc.
29.5
29.6
29.7
29.8
29.9
Output Frame Queuing...............................................................................................................................................1831
Reset and Stop Functions............................................................................................................................................1835
Firmware Architecture and Tasks...............................................................................................................................1837
FIFO Interface Data Structure....................................................................................................................................1838
Programmable Registers.............................................................................................................................................1839
29.5.1
29.5.2
29.5.3
29.5.4
29.5.5
29.5.6
29.5.7
29.6.1
29.6.2
29.6.3
29.6.4
29.6.5
29.7.1
29.7.2
29.7.3
29.9.1
Overview..................................................................................................................................................1831
Cell and Queue Concept..........................................................................................................................1832
Write Control Module.............................................................................................................................1833
Cell Factory Module................................................................................................................................1833
Output Queue Manager..................................................................................................................................?
Congestion Management.........................................................................................................................1834
Implementation Notes.............................................................................................................................1834
Stop Controls...........................................................................................................................................1835
Port Disable.............................................................................................................................................1835
Port 0 Input Protection.............................................................................................................................1836
Port 1,2 Input Protection..........................................................................................................................1836
DMA Bus Error.......................................................................................................................................1836
Overview..................................................................................................................................................1837
Firmware Environment............................................................................................................................1837
Firmware Overview.................................................................................................................................1837
ENET SWI revision (HW_ENET_SWIREVISION)..............................................................................1845
29.4.10.8
29.5.5.1
29.5.5.2
29.7.3.1
29.7.3.2
29.7.3.3
29.7.3.4
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Switching..............................................................................................................................1831
Overview...............................................................................................................................1833
Weighted Fair Queuing scheduling algorithm......................................................................1834
Application Main..................................................................................................................1837
Learning Task........................................................................................................................1837
Timer Task.............................................................................................................................1837
Aging Task............................................................................................................................1838
Title
Page
67
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