MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 867

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.8.8 APBX Clock Control Register (HW_CLKCTRL_XBUS)
This register controls the clock divider that generates the CLK_X, the clock used by the
APBX bus. Note: Do not write register space when busy bit(s) are high.
EXAMPLE
HW_CLKCTRL_XBUS_WR(BF_CLKCTRL_XBUS_DIV(4)); // set apbx xbus clock to 1/4 the 24.0MHz crystal
Address:
Freescale Semiconductor, Inc.
Reset
Reset
clock frequency
AUTO_CLEAR_
DIV_FRAC_EN
DIV_ENABLE
Bit
Bit
W
W
RSRVD1
R
R
30 12
BUSY
Field
Field
4 0
DIV
BUSY
31
11
5
31
15
0
0
RSRVD1[15:12]
HW_CLKCTRL_XBUS
30
14
0
0
1 = Enable fractional divide. 0 = Enable integer divide.
CLK_P-to-CLK_H divide ratio.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0.
This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
clock domains.
Always set to zero (0).
If this bit is set to one (1'b1), HW_CLKCTRL_XBUS_DIV is cleared to 1 automaticlly without S/W interaction
when wakeup interrupt event happens. This feature is to accelerate the waking up from Wait-For-Interrupt
Mode.
Note: This bit is not self-cleared. This feature is supposed to used when the clk_x is reduced to very low
frequency, for example, 24KHz.
29
13
0
0
HW_CLKCTRL_HBUS field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_CLKCTRL_XBUS field descriptions
8004_0000h base + 70h offset = 8004_0070h
27
11
0
0
26
10
0
0
25
0
0
9
24
0
1
RSRVD1[30:16]
8
Description
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
23
0
0
7
22
0
0
6
21
0
5
0
DIV
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
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