MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2061
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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After the RGB to RGB or RGB to YCbCr 4:2:2 color space conversions, there is one more
opportunity to swizzle the data before sending it out to the display or the encoder. This can
be done with the CSC_DATA_SWIZZLE field in the HW_LCDIF_CTRL register, and it
provides the same options as the INPUT_DATA_SWIZZLE register.
Finally, there is an option to shift the output data before sending it out to the display. This
is done based on the SHIFT_DIR and SHIFT_NUM_BITS fields in HW_LCDIF_CTRL
register.
Figure 33-2
The examples in
programming for write mode. Assume that the data written into the HW_LCDIF_DATA
register is of the format {A7–A0, B7–B0, C7–C0, D7–D0} in 8-bit mode and {A15–A0,
B15–B0} in 16-bit mode.
Freescale Semiconductor, Inc.
• YCBCR422_INPUT=1 implies that the input frame is in YCbCr 4:2:2 format.
• ODD_LINE_PATTERN and EVEN_LINE_PATTERN must be 0 when any of
AXI MST
Limitation: If BYTE_PACKING_FORMAT [3:0] is 0xF, it indicates that the pixels
are packed, that is, there are 4 pixels in 3 words or 12 bytes and H_COUNT must be a
multiple of 4 pixels.
BYTE_PACKING_FORMAT must be 0xF.
Limitation: LCD_DATABUS_WIDTH must be 8-bit and H_COUNT must be a multiple
of 2 pixels.
RGB_TO_YCBCR422_CSC or INTERLACE_FIELDS or YCBCR422_INPUT bits
is 1.
Control
Packing
shows the general operations that occur in the write data path.
Byte
Xmit Data
64
FIFO in Byte Enables
Figure 33-3
8
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Swizzle
8
64
Figure 33-2. LCDIF Write Data Path
Count
Calcn
–
Write Control
Figure 33-6
FIFO Status
8
LFIFO
256
76x
76
38
Serialize,
888 CSC
Delta
Pixel
Unpack
& RGB
to RGB
illustrate some different combinations of register
38
38
IntFIFO
38x2
38
FIFO Status
RGB to
YCbCr
4:2:2
Domain
HCLK
MPU/VSYNC/
DOTCLK/DVI
Mode Control
38
TxFIFO
38x16
CLK_DIS_LCDIFn
Control
Read
32
4
Domain
Chapter 33 LCD Interface (LCDIF)
Transfer
Control
32
Signal
Gen
8/16/18/24
Shift
LCD Control
8/16/18/24
LCD Data
2061
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