MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2202

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
35.2 Operation
The SAIF is a half-duplex port, meaning it can either transmit or receive PCM audio, but
not simultaneously. (Full-duplex support is availabe with two SAIF modules: one transmits
while the other receives.) Data is communicated serially one sample at a time, alternating
between left and right samples. One to three serial data lines (SDATA0–SDATA2) can be
used to transmit either two (stereo/mono), four (stereo/surround), or six
(stereo/surround/center/LFE) channels of digital PCM audio data. Samples boundaries are
delineated by a left/right clock (LRCLK) pin, and individual bits within each sample are
delineated by a bit clock (BITCLK) pin.
The LRCLK can be programmed to toggle every 16, 24, or 32 BITCLK transitions, and,
because data ranges from 16 to 24 bits, serial data within each LRCLK period can either
fully occupy the LRCLK cycle or cause the LRCLK period to contain BITCLK cycles in
which no data is being communicated. Because of this, three basic types of sample frame
formats can be programmed: I
programming options exist to alter these basic frame types, such as the LRCLK signal
polarity, BITCLK edge selection to drive/sample serial data, and sample justification/delay
within an LRCLK period.
2202
Figure 35-1. Serial Audio Interface (SAIF) Block Diagram
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
APBX
Interface
Registers
DMA
Control
Frame
Serial
FIFOs
2
S, left-justified, and right-justified. However, many
Front
BITCLK/
Dividers
LRCLK
MCLK/
1, 2, or 3
Surround
saif_clk
Center/
LFE
CLKCTRL
SAIF_LRCLK Pin
SAIF__MCLK_BITCLK Pin
SAIF_ALT_BITCLK Pin
(IFRAC reg)
SAIF_SDATA Pins
Freescale Semiconductor, Inc.