MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1102

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

DDR PHY
The io_dqs_out and the emi_clk are edge-aligned in this EMI design. This help to meet the
tDQSS timing requirement defined by DRAM device.
The io_dqs_out and the io_dq_out are center-aligned which is required by the DRAM
device.
14.7.8 Write Data Path Low-Latency Option
In the example of
1/4 cycle for data d0, which is critical in timing.
This DDR_PHY provides two write data path options for the user :
14.7.9 Digital DLL and the Delay-Line
Due to the asynchronous nature of the DRAM devices, the timing requirements for capturing
and receiving data between the i.MX28 and the DRAM devices must be addressed. This
EMI contains a circuit that, in conjunction with I/O cell circuitry, can be used to meet the
timing requirements for DRAM devices. The delay compensation circuit was designed with
the following features:
1102
• The Standard Latency option.
• The Low-Latency option.
• Programmable read strobe delay specified as a percentage of a clock cycle.
An extra latch at emi_clk domain is asserted into the write data path, right ahead of the
latch at clk_wr domain (at the place of marker 1 in
asserted-latch and the latch at clk_wr are put back-to-back. The total delay in write data
path is 1 + 1/4 cycle.
It is safe in timing, but decreases performance by adding one cycle of latency.
The asserted latch for standard-latency is bypassed. The total delay in write data path
is 1/4 cycle.
There is risk in the timing of the write data path, but it has higher performance than the
standard-latency case.
The marker 1 emphasizes that the setup time here for data d0 is
only 1/4 cycle, that would be critical in timing.
Low-Latency Option
Figure
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
14-12, note the marker 1. It emphasizes that the setup time is only
provides more details.
NOTE
Figure
Write Data Path
14-12). By this means, the
Freescale Semiconductor, Inc.