MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 373

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.5.9 APBH DMA Channel 0 Next Command Address Register
The APBH DMA Channel 0 Next Command Address register contains the address of the
next multiword command to be executed. Commands are threaded on the command address.
Set CHAIN to 1 in the DMA command word to process command lists.
APBH DMA Channel 0 is controlled by a variable sized command structure. Software loads
this register with the address of the first command structure to process and increments the
Channel 0 semaphore to start processing. This register points to the next command structure
to be executed when the current command is completed.
EXAMPLE
HW_APBH_CHn_NXTCMDAR_WR(0, (reg32_t) pCommandTwoStructure);
BF_WRn(APBH_CHn_NXTCMDAR, 0, (reg32_t) pCommandTwoStructure);
HW_APBH_CHn_NXTCMDAR(0).CMD_ADDR = (reg32_t) pCommandTwoStructure;
Address:
Re-
6.5.10 APBH DMA Channel 0 Command Register (HW_APBH_CH0_CMD)
The APBH DMA Channel 0 command register specifies the DMA transaction to perform
for the current command chain item.
The command register controls the overall operation of each DMA command for this channel.
It includes the number of bytes to transfer to or from the device, the number of APB PIO
command words included with this command structure, whether to interrupt at command
completion, whether to chain an additional command to the end of this one and whether
this transfer is a read or write DMA transfer.
Freescale Semiconductor, Inc.
set
Bit
W
since there is only one field
bitfield write macro
of indexed register's struct
R
CMD_ADDR
31
0
Field
31 0
30
0
(HW_APBH_CH0_NXTCMDAR)
29
0
HW_APBH_CH0_NXTCMDAR
28
0
Pointer to next command structure for channel 0.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_APBH_CH0_NXTCMDAR field descriptions
24
0
23
0
22
0
21
0
20
0
8000_4000h base + 110h offset = 8000_4110h
19
0
18
0
17
CMD_ADDR
0
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
// write the entire register,
0
9
// or, use multi-register
// or, assign to bitfield
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
373
0
0