MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2089

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor, Inc.
READ_PACK_DIR
OUTSTANDING_
BURST_LEN_8
READ_MODE_
RGB_FORMAT
OUTPUT_IN_
EVEN_LINE_
ODD_LINE_
PATTERN
PATTERN
RSRVD5
RSRVD4
RSRVD3
RSRVD2
REQS
31 24
23 21
18 16
14 12
Field
20
19
15
11
10
9
Reserved bits. Write as 0.
This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when
it is acting as a bus master. Default is 2 outstanding transactions.
0x0
0x1
0x2
0x3
0x4
By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when
in packed 24 bpp mode, it will issue bursts of length 15). When this bit is set to 1, the block will issue bursts
of length 8 (except when in packed 24 bpp mode, it will issue bursts of length 9). Note that this bitfield is
only applicable when LCDIF_MASTER is set to 1.
Reserved bits. Write as 0.
This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,..).
This bitfield must be 0 in DVI mode.
0x0
0x1
0x2
0x3
0x4
0x5
Reserved bits. Write as 0.
This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,..).
This bitfield must be 0 in DVI mode.
0x0
0x1
0x2
0x3
0x4
0x5
Reserved bits. Write as 0.
The default value of 0 indicates data is stored in the little endian format. When LCD_DATABUS_WIDTH
is 8-bit, this bit provides the option of rearranging the data byte-wise in the big endian format. For example,
if READ_MODE_NUM_PACKED_SUBWORDS = 3 and the order of incoming data is 0x11, 0x22 and 0x33,
then setting this bit to 1 will cause the data to be stored as 0x00112233 as opposed to the default
0x00332211. This operation occurs after the shifting operation done by SHIFT_NUM_BITS bitfield.
Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by
WORD_LENGTH bitfield. This feature is not available when WORD_LENGTH is set to 8 bits. LCDIF
performs this operation of converting to RGB format after the endianness has been determined by the
READ_PACK_DIR bitfield.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
REQ_1 —
REQ_2 —
REQ_4 —
REQ_8 —
REQ_16 —
RGB —
RBG —
GBR —
GRB —
BRG —
BGR —
RGB —
RBG —
GBR —
GRB —
BRG —
BGR —
HW_LCDIF_CTRL2 field descriptions
Description
Chapter 33 LCD Interface (LCDIF)
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