MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 349

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

When the last DMA command of an atomic sequence is completed, the lock should be
removed. To accomplish this, the last command does not have the NAND_LOCK bit. It is
still locked in the atomic state within the arbiter when the command starts, so that it is the
only NAND command that can be executed. At the end, it drops from the atomic state within
the arbiter.
The NAND_WAIT4READY bit also has a special use for DMA channels (from channel 4
to channel 11), that is, the NAND device channels. The NAND device supplies a sample
of the ready line for the NAND device. This ready value is used to hold off of a command
with this bit set until the ready line is asserted to 1. Once the arbiter sees a command with
a wait-for-ready set, it holds off that channel until ready is asserted.
Receiving an IRQ for HALTONTERMINATE (HOT) is a new feature in the APBH/X
DMA descriptor that allows certain peripheral block (for example, GPMI, SSP, I2C) to
signal to the DMA engine that an error has occurred. In prior chips, if a block is stalled due
to an error, the only practical way to discover this in software was through a timer of some
sort, or to poll the block. Now, an HOT signal is sent from the peripheral to the DMA engine
and causes an IRQ after terminating the DMA descriptor being executed. Note not all
peripheral block support this termination feature.
Therefore, it is recommended that software use this signal as follows:
Each channel has an eight-bit counting semaphore that controls whether it is in the run or
idle state. When the semaphore is non-zero, the channel is ready to run, process commands
and perform DMA transfers. Whenever a command finishes its DMA transfer, it checks
the DECREMENT_SEMAPHORE bit. If set, it decrements the counting semaphore. If the
semaphore goes to 0 as a result, then the channel enters the IDLE state and remains there
until the semaphore is incremented by the software. When the semaphore goes to non-zero
and the channel is in its IDLE state, then it uses the value in the
HW_APBH_CHn_NXTCMDAR register (next command address register) to fetch a pointer
Freescale Semiconductor, Inc.
• Always set HALTONTERMINATE to 1 in a DMA descriptor. That way, if a peripheral
• When an IRQ from an APBH/X channel is received, and the IRQ is determined to be
signals HOT, the transfer will end, leaving the peripheral block and the DMA engine
synchronized (but at the end of a command).
due to an error (as opposed to an IRQONCOMPLETE interrupt) the software should:
• Reset the channel.
• Determine the error from error reporting in the peripheral block, then manage the
error in the peripheral that is attached to that channel in whatever appropriate way
exists for that device (software recovery, device reset, block reset, and so on).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
349