MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1314

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Frame Format for SPI and SSI
The frequency of the output signal bit clock SSP_SCK is defined as follows:
SSP _ SCK =
For example, if SSPCLK is 3.6864 MHz, and CLOCK_DIVIDE = 2, then SSP_SCK has
a frequency range from 7.2 KHz to 1.8432 MHz. See
(CLKCTRL) Overview
17.4 Frame Format for SPI and SSI
Each data frame is between 4 and 16 bits long, depending on the size of data programmed,
and is transmitted starting with the MSB. Two basic frame types can be selected:
For both formats, the serial clock (SSP_SCK) is held inactive while the SSP is idle and
transitions at the programmed frequency only during active transmissions or reception of
data. The idle state of SSP_SCK is used to provide a receive time-out indication, which
occurs when FIFO still contains data after a time-out period.
For Motorola SPI frame format, the serial frame (SSn) pin is active low and is asserted
(pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial interface (SSI) frame format, the SSn pin is pulsed
for one serial clock period starting at its rising edge, prior to the transmission of each frame.
For this frame format, both the SSP and the off-chip slave device drive their output on data
on the rising edge of SSP_SCK, and latch data from the other device on the falling edge.
The SSP master supports up to three combinations of SPI and SSI slave devices connected.
Three SSn pins are provided but only one can be active at a time.
17.5 Motorola SPI Mode
The SPI mode is used for general inter-component communication and legacy 1-bit MMC
cards.
1314
• Motorola SPI
• Texas Instruments Synchronous Serial Interface (SSI)
CLOCK DIVIDE × (1 + CLOCK _ RATE)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
SSPCLK
for more clock details.
Clock Generation and Control
Freescale Semiconductor, Inc.